obione (18-11-2020)
MS x64 emulation Windows ARM...
. ( ARM Mac Virtualization, = VM Parallels/Fusion, bootcamp Windows x64)
ARM Mac "" / ARM (x64) Windows!
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x64 windows arm.
apple. chip ... MacPro ...
panos74gr (23-11-2020)
Valkyre (23-11-2020)
^^ chipset MacPro.
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royalties... . apple "" ...
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;
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: SoC!!!!!
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.
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Sorry , !!!!
Last edited by nikosarg; 23-11-2020 at 14:36.
gRim (24-11-2020),Lefteris_X (23-11-2020),Slay (23-11-2020),Stefanos (23-11-2020),Valkyre (25-11-2020)
psx3 (25-11-2020)
nikosarg.
x86 RISC (out-of-order execution, load/store .), frontend (decoder/), /opcodes ( legacy cruft).
boot 16-bit/real mode BC. BIOS UEFI. Legacy cruft 40 . DOS, .
(assembly) compiler (C/C++) /registers ( CPU).
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RISC on steroids load/store GPGPUs registers ( register files).
RISC / CISC . .
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custom NVMe 2015 (iPhone 6S).
Sony PS5. (unified RAM, dedicated co-processors, soldered DRAM, NAND, / software stack .)
Intel.
( ) ARM ; XScale 1 iPhone (post-PC era).
.
. 2020 inefficient 14nm .
MS Ballmer mobile computing (PDA, UMPC, Nokia, WinCE/Windows Mobile/Phone).
(Wintel) 80s/90s ( ARM Apple), 2000s/2010s.
Last edited by psx3; 25-11-2020 at 01:01.
Lefteris_X (25-11-2020),nikosarg (25-11-2020),Slay (25-11-2020)
Mac chip. reviewers unified memory iOS .
SSD controller , benchmarks iPad Pro virtual memory management Mac OS . Mac OS hardware compression virtual memory, .
iOS virtual memory. virtual memory app apps background device.
SDK memory mapping ( ) application . photos 120fps iPad Pro frame drops.
Sorry . , ,
Why Cant Intel and AMD Add More Instruction Decoders?
This is where we finally see the revenge of RISC, and where the fact that the M1 Firestorm core has an ARM RISC architecture begins to matter.
You see, for x86 an instruction can be anywhere from 1–15 bytes long. On a RISC chip instructions are fixed size. Why is that relevant in this case?
Because splitting up a stream of bytes into instructions to feed into 8 different decoders in parallel becomes trivial if every instruction has the same length.
However on an x86 CPU the decoders have no clue where the next instruction starts. It has to actually analyze each instruction in order to see how long it is.
The brute force way Intel and AMD deal with this is by simply attempting to decode instructions at every posssible starting points. That means we have to deal with lots of wrong guesses and mistakes which has to be discarded. This creates such a convoluted and complicated decoder stage, that it is really hard to add more decoders. But for Apple it is trivial in comparison to keep adding more.
In fact adding more causes so many other problems that 4 decoders according to AMD itself is basically an upper limit for how far they can go.
This is what allows the M1 Firestorm cores to essentially process twice as many instructions as AMD and Intel CPUs at the same clock frequency.
One could argue as a counterpoint that CISC instructions turn into more micro-ops, that they are denser so that e.g. decoding one x86 instruction is more similar to decoding say two ARM instructions.
Except this is not the case in the real world. Highly optimized x86 code rarely use the complex CISC instructions. In some regards it has a RISC flavor.
But that doesnt help Intel or AMD, because even if those 15 byte long instructions are rare, the decoders have to be made to handle them. This incurs complexity which blocks AMD and Intel from adding more decoders.
But AMDs Zen3 Cores are Still Faster Right?
As far as I remember from performance benchmarks the newest AMD CPU cores, the ones called Zen3 are slightly faster than Firestorm cores. But here is the kicker, that only happens because the Zen3 cores are clocked at 5 GHz. Firestorm cores are clocked at 3.2 GHz. The Zen3 is just barely squeezing past Firestorm despite having almost 60% higher clock frequency.
Last edited by nikosarg; 02-12-2020 at 22:09.
psx3 (02-12-2020)
! , 90, risk cisc. RISC .
( 1 ) license custom ARM cores Apple (.. nVidia);
. nVidia ( ?) ARM royalties Apple custom ARM IP .
Apple nVidia ( Apple , ) Tegra SoC (automobile, consoles). Win-win.
AMD semi-custom APUs ...
, ( Apple), ( )!
( ):
https://medium.com/swlh/pc-users-in-...e-373cbf7c9d5d
https://medium.com/macoclock/how-app...h-c63f60275f59
:
( disruptive innovation)... PCMR - - rigs 500-600W full load /!What about x86 Gaming Rig PCs?
It will be interesting to see how the gaming-rig market develops. The system on a chip (SoC) trend will mean custom built rigs with external graphics cards may no longer be able to compete.
Nvidia is on top of this trend as well, as can be seen from the purchase of ARM. They will likely being creating ARM based SoCs which gamers will start switching to, for max performance in first person shooter games.
In the iPhone analogy, Nvidia may be the Samsung/Google of the PC world. Old players such as Intel and AMD may get squeezed out while new players like Nvidia enters.
There could be more innovative or smaller players in the PC industry that make a bold bets on Nvidia ARM SoC solutions and steal a lot of marketshare from established players like Dell and HP. This could be companies like ASUS or some other Asian manufacturer who is looking for some big change they can exploit to get an upper hand on the current dominant players.
Last edited by psx3; 03-12-2020 at 15:27.
nikosarg (03-12-2020)
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